1. Field of the Invention
The present invention relates generally to PLL (phase locked loop) circuits and, more particularly, to a digital signal processing-type PLL circuit for extracting a clock from input digital data.
2. Description of the Prior Art
In the case of recording and reproducing apparatus that can record and reproduce digital data such as a digital audio signal or the like on and from a magnetic tape, in order to detect digital data reproduced from the magnetic tape upon playback, the reproduced signal is supplied to a PLL (phase locked loop) circuit and a clock contained in the reproduced data is extracted by the PLL circuit, whereby recorded data is detected in synchronism with the clock thus extracted.
The conventional PLL circuit that extracts the clock from the reproduced signal is formed of a circuit for performing analog processing. The analog PLL circuit must adjust a free running frequency in order to absorb irregular characteristics of circuit elements when it is assembled into a reproducing apparatus or the like. Also, the conventional analog PLL circuit has poor temperature characteristics and has an aging change. Further, the analog PLL circuit is quite easily affected by noise in the voltage-controlled oscillator (VCO) that constructs the PLL circuit. If an offset occurs in a phase of a reproduced clock due to the above-mentioned factors, then an error rate,of reproduced data will be deteriorated.
To remove such disadvantages, there has been developed a digital signal processing type PLL circuit (hereinafter simply referred to as a digital PLL circuit) that extracts a clock from an input signal in a digital processing fashion. U.S. Pat. No. 4,855,683, for example, describes a circuit arrangement of a digital PLL circuit having an accumulator type digital voltage controlled oscillator.
In the digital PLL circuit, a digital VCO (digital voltage-controlled oscillator), for example, is constructed by an accumulator and a phase of output data of the digital VCO formed of the accumulator and a phase of external input data are compared with each other by the calculation processing. Then, a compared result is fed back to the accumulator to thereby reproduce the clock of the external input data. According to this digital PLL circuit, a clock can be reproduced with high accuracy.
The digital PLL circuit, however, has the disadvantages such that its arrangement becomes complicated and that its electric power consumption is large.
More specifically, when the digital PLL circuit performs a digital signal processing, an analog-to-digital (A/D) converter for converting an input signal (reproduced signal) into a digital signal must be provided at the preceding stage of the digital PLL circuit. Also, digital conversion necessary for the processing in the digital PLL circuit needs high speed processing. Accordingly, a circuit scale and an electric power consumption necessary for the above conversion processing are unavoidably increased.
A master clock required by the digital PLL circuit must be made higher than a maximum frequency of an output clock in the reproduced signal, and a large electric power is required to prepare a master clock having a high frequency.
When digital data is detected from a reproduced signal reproduced from the magnetic tape, the level of the reproduced signal is considerably fluctuated due to the reproduced state (e.g., the tracking control state of the playback head) of the magnetic tape. Further, the level of reproduced signal is fluctuated when a sampling is carried out in the vicinity of a zero-cross point of reproduced data due to the change of sampling phase upon digital conversion of the reproduced data or when the sampling is carried out at other portions.
The processing within the digital PLL circuit needs a clock whose frequency is as high as some integer times the frequency of the output clock. There is then the disadvantage that a clock frequency of the system is limited. If a data transmission rate of an input signal (reproduced signal) to the digital PLL circuit is fluctuated such as when a reproducing speed of the magnetic tape is fluctuated, then a free running frequency is fluctuated relatively, thereby causing the error rate to be deteriorated.
Furthermore, when the clock frequency of the input signal to the digital PLL circuit is deviated from the free running frequency, there then occurs a stationary phase offset so that an offset corresponding to the deviated amount of the input frequency from the original frequency occurs in the phase of the reproduced clock. As a result, an error rate of the data is deteriorated.